The present invention is generally related to data communications and in particular to synchronous serial communications.
Generally, serial communication of data requires coordination between a sender and a receiver. For example, typically it is necessary to know when to start a transmission and when to end it, when an error occurs, when a receiver's capacity has been exceeded, and so on. Serial data transfers depend on accurate timing in order to differentiate the bits in the data stream. This timing can be achieved in one of two ways: asynchronously or synchronously.
Synchronous communication takes place between the sender and receiver operating on synchronized clocks. The clock signal for the transmission line is typically derived from the signal used for clocking internal operations of the transmitting device. That clock, in turn, is typically provided by an external oscillator; but, sometimes, it may be generated by the transmitting device's internal oscillator.
Synchronization between transmitter and receiver may be achieved either by providing both of them with a common clock coming from an external source or by passing the clock timing information from the transmitter to the receiver. In the simplest form, passing the clock timing between transmitter and receiver may be accomplished by sending the clock over a dedicated clock line. Often, the receiver uses this clock directly for clocking the received data into its registers. If this is the case, the clock and the data signals do not have to follow any periodic timing—the only requirement is that the data signal is stable around the time when the receiver, directed by the clock, is sampling it.
Alternatively, the receiver uses the provided clock as a reference signal for its internal phase-locked loop which generates the receive clock.
In a more complex form, the transmit clock timing may be embedded in the transmitted data. The receiver uses the data as a reference signal for a phase-locked loop which generates the receive clock. Such a solution typically involves special coding of data which guarantees that, independent of the data content, the frequency of the data signal level transitions never falls below a certain minimum which is needed for proper operation of the phase-locked loop.
As the name implies, asynchronous communication is performed between two (or more) devices which operate on independent clocks. Therefore, even if the two clocks agree for a time, there is no guarantee that they will continue to agree over extended periods. Yet, for data communication with no errors, the communicating devices must guarantee that when device A begins and ends transmitting, device B begins and ends receiving. The receiving device alone must determine the best time to sample the incoming data signal, based on its own clock and level transitions detected in the incoming data. Consequently, asynchronous communication is typically relegated to slow speed devices.
By contrast, synchronous communication, although more complicated to implement by virtue of the requirement of a synchronized clock, can achieve higher data rates and more efficient data transfers by sending data as large blocks of information. It is therefore desirous to continue improving synchronous data communication techniques.